Layout pattern

ABSTRACT

A layout pattern is disclosed. The layout pattern includes: a polygon pattern having at least one segment; and at least one notch formed in the polygon pattern, wherein at least one side of the notch is less than the length of the segment.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. application Ser. No. 12/512,034filed Jul. 30, 2009, and incorporated herein by reference in itsentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a layout pattern, and more particularly, to alayout pattern having at least one segment that is modified through anoptical proximity correction.

2. Description of the Prior Art

Critical technologies such as the photolithography and etchingtechnologies are frequently used in semiconductor manufacturingprocesses. The photolithography technology usually involves transferringa complicated integrated circuit pattern to a semiconductor wafersurface for steps such as etching and implantation. These patterns mustbe extremely accurate for forming delicate integrated circuits so as toalign with the patterns of the previous and following steps.

In the photolithographic step, deviations often occur and jeopardize theperformance of the semiconductor device when the patterns on the masksare transferred onto the wafer surface. Such deviations are usuallyrelated with the characters of the patterns to be transferred, thetopology of the wafer, the source of the light and various processparameters.

There are many known verification methods, correction methods andcompensation methods for the deviations caused by the optical proximityeffect, process rules (PRC) and lithography rules (LRC) to improve theimage quality after transfer. Some of the known methods are calledoptical proximity correction (OPC), process rule check (PRC) andlithography rule check (LRC). The commercially available OPC softwaremay test problems such as pitch, bridge, and critical dimensionuniformity in the layout patterns. Such software may correct thestandard layout patterns on the masks using the theoretical image, so asto obtain correctly exposed image patterns on the wafers. Such methodsnot only test problems in the layout patterns but also correct thelayout patterns on the masks using the theoretical image. If thecorrected image patterns are useable, they are output for thefabrication of masks to obtain the correct image patterns on the wafer.

Generally speaking, there are well-established stand operationalprocedures available for the reference of the above-mentionedverification, correction and compensation methods. For example, theconventional procedure using optical proximity correction to verify thelayout patterns on a mask may be first inputting a layout pattern. Thenthe Boolean pre-treatment of OPC is performed on the layout pattern toobtain a preliminary layout pattern. An OPC is conducted thereafter byusing a variety of commercial optical proximity correction software,which can correct the mask pattern theoretically to acquire more correctpattern on a wafer.

A mask pattern corrected by the optical proximity correction must beinspected by a process rule check (PRC) to confirm the correctness ofthe mask pattern. If the corrected mask pattern completely obeys therules of the process rule check, the mask pattern is then output andprovided to a mask for lithography process. Conversely, if a portion orall portions of the mask pattern violates the rules of process rulecheck, the mask pattern needs to be re-modified and verified. Theprocess rule check (PRC) inspects line ends and corners of each segmentof a mask pattern to verify that if those geometrical patterns obey thelimitation of the critical width and the critical space of the designedintegrated circuit layout.

However, the aforementioned inspection typically inspects a targetpattern from a 45 degree approach, such as from 0-45 degree, 45-90degree, 90-135 degree, or 135-180 degree. The 45 degree based inspectionoften creates a blind spot between every 45 degree angle and limits thecorrection process from outputting a precise layout pattern.

SUMMARY OF THE INVENTION

It is an objective of the present invention to provide a method forcorrecting layout pattern for reducing blind spot issue caused byconventional 45 degree inspection approach.

According to a preferred embodiment of the present invention, a methodfor correcting layout pattern is disclosed. The method includes thesteps of: providing a layout pattern having at least one segment;forming a rule-checking rectangle from the segment, wherein therule-checking rectangle comprises at least one square; verifying whetherthe square of the rule-checking rectangle overlaps other layout pattern;removing the portion of other layout pattern overlapped by the square toobtain a corrected layout pattern; and outputting the corrected layoutpattern to a mask.

According to another aspect of the present invention, a method forcorrecting layout pattern is disclosed. The method includes the stepsof: providing a layout pattern having at least one segment; forming arule-checking rectangle from the segment, wherein the rule-checkingrectangle comprises at least one square; verifying the region exceededby the square while overlapping the layout pattern with the square;reinstating the region exceeded by the square to obtain a correctedlayout pattern; and outputting the corrected layout pattern to a mask.

According to an embodiment of the present invention, a layout pattern isdisclosed. The layout pattern includes: a polygon pattern having atleast one segment; and at least one notch formed in the polygon pattern,wherein at least one side of the notch is less than the length of thesegment.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart illustrating a method of correcting a layoutpattern of the present invention.

FIG. 2 illustrates a method for performing an outward correctionaccording to a preferred embodiment of the present invention.

FIG. 3 illustrates a perspective view of the layout pattern obtainedafter an outward correction.

FIG. 4 illustrates a method of performing an inward correction accordingto a preferred embodiment of the present invention.

FIG. 5 illustrates a perspective view of the layout pattern obtainedafter an inward correction.

DETAILED DESCRIPTION

Referring to FIG. 1, FIG. 1 is a flow chart illustrating a method ofcorrecting a layout pattern of the present invention. The method ofverifying a layout pattern includes following steps. First, step 10 iscarried out to input a preliminary layout pattern from a computersystem, in which the layout pattern includes at least a segment. Thelayout pattern has preferably been corrected at least once by an opticalproximity correction in the aforementioned computer system or othercomputer systems. The optical proximity corrections are prevalentcorrection methods used to modify widths, line ends and corners of eachsegment of a layout pattern in semiconductor industry. Next, step 12 iscarried out to input a process rule. The process rule includes thecritical width and the critical space or other design rules, which mayderivate from the integrated circuits of the line width of 65 nm, 45 nmor below. Afterwards, step 14 is carried out to select a target segmentand expand a rule-checking rectangle from the target segment, and averification is conducted through the rule-checking rectangle, as shownby step 16. If the verification is complete, such as the process rule issatisfied, step 22 is carried out to output a verified layout patternfrom the computer system. The verified layout pattern is preferably usedto fabricate a mask utilized in a lithography process later on. However,if the verification fails, the computer system would provide acorrecting value to perform an inward correction of step 18 or anoutward correction of step 20 from the segment. Finally, step 22 iscarried out to output the corrected layout patterns for fabricatingdesirable masks.

Referring to FIG. 2, FIG. 2 illustrates a method for performing anoutward correction according to a preferred embodiment of the presentinvention. As shown in FIG. 2, a preliminary layout patter 32, such as apattern being processed through optical proximity process and Booleanprocess is provided. For sake of brevity, only a portion of the layoutpattern 32 is shown in the figure. The aforementioned optical proximitycorrection is a common technique widely used in today's industries,which preferably corrects the width of each segment, end of the straightline, and various corners of a layout pattern. The layout pattern 32 ofthis embodiment is preferably a mask pattern utilized for fabricatingtrenches, contact vias, or polysilicon gates of a semiconductor device,and the layout pattern 32 could be a clear tone or a dark tone regionaccording to the demand of the process.

A segment 34 is then selected from the layout pattern 32, and arule-checking rectangle 36 containing at least one square is expandedoutward from the segment 34. In this embodiment, the segment 34 ispreferably the end portion of the layout pattern 32 adjacent to otherlayout pattern, and the rule-checking rectangle 36 is preferablycomposed of a rectangle 38 and two squares 40 formed at two ends of therectangle 38. The length of the rectangle 38 is preferably equivalent tothe length of the segment 34, and the width of the rectangle 38 and onesides of the square 40 is assigned as a minimum space according to amask rule check (MRC) specification.

Next, each square 40 and rectangle 38 within the rule-checking rectangle36 is verified to be whether overlapping other adjacent layout pattern.In this embodiment, the square 40 on top is determined to be overlappinga portion of an adjacent layout pattern 42. As the overlapping regionexceeds the minimum space defined by the mask rule check specification,this overlapping region is assigned as a minimum space violation region44. In order to satisfy the space specification defined, the minimumspace violation region 44 generated during outward correction must beremoved before forming a desirable layout pattern. After removing thisminimum space violation region 44, a corrected layout pattern 42 isobtained.

Similar to the outward correction of the layout pattern 32, anotheroutward correction could be conducted from the layout pattern 42. Asshown in FIG. 2, a segment 46 is selected from the layout pattern 42,and a rule-checking rectangle 52 containing a rectangle 48 and twosquares 50 is expanded outward from the segment 46. The squares 50 andthe rectangle 48 of the rule-checking rectangle 52 are then verified tobe whether overlapping any adjacent layout pattern, and if anoverlapping is confirmed, the overlapped portion of the layout patternis assigned as the minimum space violation region. In this embodiment,the bottom square 50 is overlapping a portion of the adjacent layoutpattern 32, hence the portion of the layout pattern 32 overlapped by thesquare 50 is assigned as a minimum space violation region 54. Theminimum space violation region 54 of the layout pattern 32 is removedthereafter and a corrected pattern 32 is output to complete the outwardcorrection process.

Despite the embodiment illustrated in FIG. 2 involves an outwardcorrection from the layout pattern 32 to the layout pattern 42 andanother outward correction from the layout pattern 42 to the layoutpattern 32, the single outward correction performed from the layoutpattern 32 to the layout pattern 42 should already satisfy the minimumspace defined by the mask rule check specification. In other words, asthe segment 46 used by the layout pattern 42 for performing theaforementioned outward correction is the segment 46 of the preliminarylayout pattern 42, if another outward correction is conducted from thelayout pattern 42 to the layout pattern 32 after the outward correctionperformed by the layout pattern 32 to the layout pattern 42, thecorrected layout pattern would be substantially smaller than the spacedefined by the mask rule specification. Therefore, the parameters of themask rule correction specification could be adjusted before thecorrection to determine whether a single or multiple corrections is tobe conducted.

Referring to FIG. 3, FIG. 3 illustrates a perspective view of the layoutpattern obtained after an outward correction. As shown in FIG. 3, thecorrected layout pattern 32/42 is composed of primarily of a polygonpattern, in which each polygon pattern includes a segment 34′/46′utilized for generating a rule-checking rectangle. As the layout pattern32/42 of this embodiment is corrected through an outward correction, asubstantially rectangular notch 56 is preferably formed in the correctedlayout pattern 32/42 corresponding to the location of the minimum spaceviolation region 54/44 removed previously in FIG. 2. In this embodiment,at least one side of the notch is less than the length of the segment34′46′, and the length of the segment 34′/46′ is preferably between 60nm to 70 nm, but not limited thereto. In the outward correction of thisembodiment, a correction is preferably made from each layout pattern toother adjacent layout patterns according to a mask rule correctionspecification.

Referring to FIG. 4, FIG. 4 illustrates a method of performing an inwardcorrection according to a preferred embodiment of the present invention.First, a layout pattern 62 is input in a computer system, in which thelayout pattern 62 is preferably a pattern that has been processedthrough Boolean pre-treatment in the optical proximity correction stage.For sake of brevity, only a portion of the layout pattern 62 is shown inthe FIG. 4.

A segment 64 is then selected from the layout pattern 62, and arule-checking rectangle 66 containing at least a square is expandedinward from the segment 64. In this embodiment, the segment 64 ispreferably an in-corner portion of the layout pattern 62 or asubstantially narrower portion of the pattern 62, and the rule-checkingrectangle 66 is preferably composed of two squares 68. The length of thesegment 64, such as the length of each side of the square 68 is assignedas a minimum width according to a mask rule check specification.

Next, a verification is conducted to determine whether any region iscovered by the square 68 that does not belong to the layout pattern 62while the layout pattern 62 is overlapped by the square 68 of therule-checking rectangle 66. In other words, any region exceeded by thesquare 68 as the square 68 overlaps the layout pattern 62 is inspected.In the layout pattern 62 of this embodiment, despite the major portionof the square 68 and the layout pattern 62 overlap each other, a smallregion located on the top right corner of the rule-checking rectangle 66not belonging to the layout pattern 62 is overlapped by the square 68.As this region covered by the square 68 surpasses the minimum widthdefined by the mask rule correction specification, this region isassigned as a minimum width violation region 70. In order to satisfy thewidth specification defined, the minimum width violation generatedduring inward correction must be reinstated before forming a desirablelayout pattern. Next, the minimum width violation region 70 ispreferably reinstated to complete the inward correction process and thecorrected layout pattern is output thereafter.

Referring to FIG. 5, FIG. 5 illustrates a perspective view of the layoutpattern obtained after an inward correction. As shown in FIG. 5, thecorrected layout pattern 62 is composed of a polygon pattern, in whichthe polygon pattern includes a segment 64 used for generating arule-checking rectangle. As the layout pattern 62 of this embodiment iscorrected through an inward correction, a block 72 protruding from thepreliminary layout pattern 62 corresponding to the position of theaforementioned minimum width violation region is observed. The block 72is preferably rectangular, but not limited thereto. In this embodiment,at least one side of the block 72 is less than the length of the segment64, and the length of the segment 34′/46′ is preferably between 60 nm to70 nm, but not limited thereto. In the inward correction of thisembodiment, a corner of the layout pattern is preferably selected toperform a corresponding correction to another corner of the same layoutpattern. For instance, as revealed in FIGS. 4-5, an inward correction isconducted from the in-corner segment 64 of the layout pattern 62.Similarly, a corresponding inward correction could be done from the outcorner segment (adjacent to the block 72) of the layout pattern 62 tothe in-corner region, which is also within the scope of the presentinvention.

It should be noted even though outward correction and inward correctionare discussed separately in the aforementioned embodiments, in actualpractice the order and types of correction could be adjusted accordingto the property of the layout pattern. For instance, the presentinvention could conduct only the outward correction, only the inwardcorrection, or conduct both corrections sequentially, such as performingan outward correction and then an inward correction, or performing aninward correction and then an outward correction. If only an outwardcorrection is conducted, the final corrected layout pattern ready foroutput would equal to the preliminary layout pattern (one beingprocessed through Boolean pre-treatment of OPC stage) minus the minimumspace violation region; if only an inward correction is conducted, thecorrected layout pattern ready for output would equal to the sum of thepreliminary layout pattern (one being processed through Booleanpre-treatment of OPC stage) and the minimum width violation region; andif both corrections are conducted, the final corrected layout patternwould equal to the preliminary layout pattern minus the minimum spaceviolation region and plus the minimum width violation region. Accordingto another embodiment of the present invention, a reverse tone stepcould be carried out before the correction is conducted. For instance,if the preliminary layout pattern is a dark tone pattern, a reverse tonestep preferably changes the dark tone pattern to a clear tone patternwhile the surrounding clear tone pattern region is changed to dark tonepattern, thereby increasing the flexibility of the process.

Overall, the present invention provides a method for correcting layoutpattern with no blind spot. According to a preferred embodiment of thepresent invention, a segment is selected from a layout pattern that hasbeen processed through optical proximity correction, and a rule-checkingrectangle containing at least one square is expanded from the segmentfor conducting an inward correction or an outward correction. In theoutward correction, the other layout pattern overlapped by the square ofthe rule-checking rectangle is assigned as a minimum space violationregion. The minimum space violation region is preferably removed tosatisfy the space defined by the mask rule correction specification. Inan inward correction, the region covered by the square of therule-checking rectangle and surpassing the preliminary layout pattern isassigned as a minimum width violation region. The minimum widthviolation region is reinstated to satisfy the width defined by the maskrule correction specification. The corrected layout patterns are outputthereafter and the corrected layout pattern is equal to the preliminarylayout pattern minus the aforementioned minimum space violation regionand plus the minimum width violation. By following this approach, a noblind spot correction could be carried out to output much more preciselayout pattern to a mask than the conventional 45 degree approach.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A layout pattern, comprising: a polygon pattern having at least onesegment; and at least one notch formed in the polygon pattern, whereinat least one side of the notch is less than the length of the segment.2. The layout pattern of claim 1, wherein the length of the segment isbetween 60 nm to 70 nm.
 3. The layout pattern of claim 1, wherein thenotch connects the segment.
 4. The layout pattern of claim 1, whereinthe notch comprises right angled segments connecting the segment.
 5. Thelayout pattern of claim 1, wherein the segment is modified through anoptical proximity correction.
 6. The layout pattern of claim 5, whereinwidths, line ends, and corners of the segment are modified through theoptical proximity correction.
 7. The layout pattern of claim 1, whereinthe polygon pattern is composed of multiple segments and each segment ismodified by an optical proximity correction.
 8. The layout pattern ofclaim 1, wherein the polygon pattern is composed of multiple segmentsand the width of each segment is modified by an optical proximitycorrection.